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Old 05-25-2006, 04:40 PM
John Larkin
Posts: n/a
Default Re: FPGA delay generator

On Wed, 24 May 2006 21:14:17 +0200, Kolja Sulimma <[email protected]>

>John Adair schrieb:
>> I don't understand where the there are issues of jitter unless you use a DCM
>> in which case you will have issues with all Xilinx FPGAs and to varying
>> extent other vendors too. The point of our board is that you can have a high
>> speed clock with low jitter and not necessarily using the DCM which does
>> have jitter of some 10s of picoseconds.

>Even with a zero jitter 1GHz clock the generated delay will jitter 1ns.
>The output will arrive anytime in a clock period, but the output will be
>generated a fixed time after a clock edge. The delay is the difference
>between input and output. It will have +-500ps error.
>The 50ps jitter in the DG535 spec really means that the delay is fixed
>with 50ps accuracy, not only that the output time can be predicted with
>50ps accuracy.

The DG535 jitter is spec'd at 60 ps trigger-to-output and is often not
that good in units I've measured. Accuracy is spec'd at +-1.5 ns,
interesting given the speed of the output edges.

I know of a few ways to get low delay jitter:

SRS generates delay using counters clocked by a crystal oscillator at
80 MHz, followed by an analog ramp vernier delay. At every trigger, a
front-end circuit measures the time offset from the trigger to the
local clock, as an analog signal, and applies it to the vernier to
correct for the 1-clock jitter. This adds a lot of insertion delay,
requires precise ramp calibrations, and has s/h drift problems for
longer delays.

Signal Recovery (formerly EG&G) uses the fiendishly clever
interrupted-ramp technique, Pepper's patent. Imagine a simple
trigger+analog-ramp+comparator delay generator, very accurate and
jitter-free for short delays. Now interrupt, freeze, the ramp for N
cycles of a crystal-controlled clock. That extends the delay by the
freeze time and adds no jitter, even though the freeze clock is
unrelated to the trigger. The only serious problem is analog drift of
the ramp capacitor during the freeze interval, similar to the SRS
drift issue.

Several companies make (or made) a number of DDGs based on starting an
oscillator at trigger time, using a digital counter for coarse delay,
and an analog vernier for fine delay. To maintain jitter performance
for long delays, the timing oscillator must be phase-locked to a good
crystal oscillator while maintaining the original phase offset. HP,
copied by LeCroy and BNC, used a heterodyne PLL technique to
accomplish this. My company uses a DSP system: after the triggered
oscillator has started, we digitize its waveform using a flash ADC
clocked by the crystal oscillator, figure out the phase difference,
and close a digital servo loop onto the oscillator. Our technique is
(he says modestly) clearly the best.

Both of these have jitters in the single digits of ps for delays into
the tens of us, and longterm jitter limited only by the phase noise of
the xo. Both use ecl for the critical signal path.

This one runs all the fast stuff through the fpga...

which adds a lot of jitter from crosstalk, ground bounce, and fpga
delay variations as a function of tiny power supply changes and
millikelvin temperature noise, still under 50 ps.


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