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Old 05-24-2006, 12:30 PM
amko
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Default Re: FPGA delay generator

If you sample the input signal with a GHz clock and use that to
generate that clock to generate a delayed ouput you are going to have
1ns jitter in your delay, don't you

Yes, it is true. But I woul like to implement oversampled method what
means four times shifted 1GHz (500MHz) clock signal. then error will be
250 ps.

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