View Single Post
  #4 (permalink)  
Old 05-24-2006, 11:58 AM
Kolja Sulimma
Posts: n/a
Default Re: FPGA delay generator

amko schrieb:
> Hello everybody,
> Currently I am designing very accurate delay generator, which will be
> based on FPGA .
> This delay generator should have similar technical requirements with
> DG535
> The major Delay Generator requirements are
> 2 ns (1ns is desired, but 2ns will be also ok) time resolution on
> delayed channel (it means that time differences between any delayed
> channels can be set in 2 ns steps)
> maximal 50 ps - 60ps (RMS) jitter on each output.
> 14 delayed ECL channels
> Two high speed (PECL) inputs (500 Mz ECL clock signal and ECL
> trigger)

How are you trying to build the delay generator?
I see immediately how you can get a resolution of 80ps in a Virtex-4,
but I fail to see you can have a low input to output jitter in a clocked
design. If you sample the input signal with a GHz clock and use that to
generate that clock to generate a delayed ouput you are going to have
1ns jitter in your delay, don't you?

Unless you are you doing something fancy like this:

Kolja Sulimma

Reply With Quote