View Single Post
  #6 (permalink)  
Old 05-10-2006, 02:34 AM
Mark McDougall
Guest
 
Posts: n/a
Default Re: PCI Express and DMA

SongDragon wrote:

> 1) device driver (let's say for linux 2.6.x) requests some

(snip snip)
> writes a zero to a register ("serviced descriptor"), telling the PCIe
> device the interrupt has been fielded.


> I have a number of questions regarding this. First and foremost, is
> this view of the transaction correct? Is this actually "bus
> mastering"? It seems like for PCIe, since there is no "bus", there is
> no additional requirements to handle other devices "requesting" the
> bus. So I shouldn't have to perform any bus arbitration (listen in to
> see if any of the other INT pins are being triggered, etc). Is this
> assumption correct?


Your description of events is pretty much correct. The exact registers
and sequencing will of course depend on your implementation of a DMA
controller.

You'll need a source register too unless the data is being supplied by a
FIFO or I/O "pipe" on the device.

"Bus mastering" is a PCI term and refers to the ability to initiate a
PCI transfer - which also implies the capability to request the bus.

In PCIe nomenclature, an entity that can initiate a transfer is referred
to as a "requestor" and you're right, there's no arbitration involved as
such. But this is the equivalent of a PCI bus master I suppose. The
target of the request is called the "completer".

This is where my knowledge of PCIe becomes thinner, as I'm currently in
the process of ramping up for a PCIe project myself. But I have worked
on several PCI projects so I think my foundations are valid.

For example, using a (bus-mastering) PCI core you wouldn't have to
'worry about' requesting the bus etc - initiating a request via the
back-end of the core would trigger that functionality in the core
transparently for you. As far as your device is concerned, you have
"exclusive" use of the bus - you may just have to wait a bit to get to
use it (and you may get interrupted occasionally). Arbitration etc is
not your problem.

> In PCI Express, you have to specify a bunch of things in the TLP
> header, including bus #, device #, function #, and tag. I'm not sure
> what these values should be. If the CPU were requesting a MEMREAD32,
> the values for these fields in the MEMREAD32_COMPLETION response
> would would be set to the same values as were included in the
> MEMREAD32. However, since the PCIe device is actually sending out a
> MEMWRITE32 command, the values for these fields are not clear to me.


This is where I'll have to defer to others...

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
Reply With Quote