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Old 05-09-2006, 04:23 PM
SongDragon
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Default Re: PCI Express and DMA

Thanks for the helpful responses from everyone.

The basic idea seems to be as follows:

1) device driver (let's say for linux 2.6.x) requests some kernel-level
physical memory
2) device driver performs MEMWRITE32 (length = 1) to a register
("destination descriptor") on the PCIe device, setting destination address
in the memory
3) device driver performs MEMWRITE32 (length = 1) to a register ("length
descriptor") on the PCIe device, setting length "N" (We'll say this also
signals "GO")
4) PCIe device sends MEMWRITE32s (each length = up to 128 bytes at a time)
to _______ (what is the destination?) until length N is reached
5) PCIe device sends interrupt (for now, let's say INTA ... it could be MSI,
though)
6) device driver services interrupt and writes a zero to a register
("serviced descriptor"), telling the PCIe device the interrupt has been
fielded.

I have a number of questions regarding this. First and foremost, is this
view of the transaction correct? Is this actually "bus mastering"? It seems
like for PCIe, since there is no "bus", there is no additional requirements
to handle other devices "requesting" the bus. So I shouldn't have to perform
any bus arbitration (listen in to see if any of the other INT pins are being
triggered, etc). Is this assumption correct?

In PCI Express, you have to specify a bunch of things in the TLP header,
including bus #, device #, function #, and tag. I'm not sure what these
values should be. If the CPU were requesting a MEMREAD32, the values for
these fields in the MEMREAD32_COMPLETION response would would be set to the
same values as were included in the MEMREAD32. However, since the PCIe
device is actually sending out a MEMWRITE32 command, the values for these
fields are not clear to me.


Thanks,

--Alex


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