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Old 05-07-2006, 04:30 PM
Weng Tianxiang
Posts: n/a
Default Re: The differences between behaviors of 'std_logic_vector' and 'unsigned'

Sorry! I found the error. The error is not related to what I have
it relates to situation:
std_logic => A(I),
In a generate loop as following:
Lable_A : for I in 0 to 3 generate
.... port map (
A => A(I),

A() must be declared as
signal A : unsigned(3 downto 0);

And it cannot be decleared as
signal A : unsigned(1 downto 0); <-- my error

Thank you.


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