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Old 05-04-2006, 11:04 AM
Rene Tschaggelar
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Default Re: Phase alignment of DCMs on different boards/devices

Dave wrote:

> Hi group,
>
> Scenario: Multiple identical boards with a Virtex-II each all being
> fed the same clock signal which is being fed to a DCM on each device.
>
> Lets assume the clock signal has no skew between the FPGAs and all
> FPGAs get powered/configured at the same time (so the clock signals
> enter the DCMs in phase).
>
> Will the DCMs achieve lock at the same time and therefore produce
> output clocks that are in phase relative to each other on all 4 FPGAs?
> Or will the lock time vary? The datasheet says anything up to for
> example 120us (for 24-30MHz input, using DLL op) but does this mean a
> potential phase difference of 120us between the outputs of the DCMs?



Don't count on them being equally fast to lock.
There is no "in phase" in distributed systems,
strictly speaking. The phase is the delay between
clock cycles, so the max phase error is plus minus
half the clock.

You can synch multiple devices to within a clock cycle,
provided the system is less distributed than a
clockcycle is fast, with a trigger pulse. To achieve better
synchronization, you need some hardware delay or PLL.
Most highend FPGAs do have internal cClock PLLs.

Rene
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