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Old 05-04-2006, 02:35 AM
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Default Re: ports of multidimentional arrays in verilog.

Write it as several 8-bit vectors or as one n*8 bit vector. You can't pass
arrays in Verilog or Verilog2001.
There's also comp.lang.verilog.

"CMOS" <[email protected]> wrote in message
news:[email protected]
> hi,
> using verilog how to write a module which has an inpput port for an
> array of 8 bit signals and how to write a test bench for it.
> thank you.

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