Stephen,

Thank you for your reply.

I am "pretty sure" my VHDL is correct, because the FSMs in the design
function correctly most of the time, and do not pre-empt the host
computer on the other end of the parallel port I'm using, which the
data buffer is connected to.

It is as though the latch and/or the IO pin does not respond to a
change in an internal signal. From what I can see on the logic
analyser, this problem sometimes persists for a long time, or until the
board is reset.

Unfortunatly, I don't have access to ChipScope, so I cannot observe the
internal signals.

I am at a loss to explain this behaviour, and of course I am open to
accepting that my VHDL is incorrect with some evidence. I am not
familiar with the ins and outs of the Virtex-II (or any FPGA really) so
there may be some small detail of which I am unaware...

The exact problem I am having is that the output enable of the
bi-directional buffer is not always set active when it should be. A FSM
in the FPGA will then read what appears to be a non-driven input. I am
happy that the test setup is OK, as the results I observe are
consistent with the behaviour resulting from incorrect data on the data
lines from the parallel port.

Have you observed similar behaviour on IO pins before?

Thanks,
Robin
University of Newcastle