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Old 05-02-2006, 11:06 PM
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Default bizzare unexplained random errors w/ Lattice 4256V CPLD

We are using VHDL on a new design with a Lattice 4256V and are running
into problems with our shift registers. We're using ispLEVER 5.1 trial
along with Synplicity synthesis. Here's our generic 11-bit shift
register with async. parallel load:

-- 11 bit shifter for data serialization
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;

entity shifter11 is
clk:in std_logic;
rst:in std_logic;
data_in:in std_logic_vector(10 downto 0);
shift_load_select:in std_logic;
shift_in:in std_logic;
data_outut std_logic);
end shifter11;

architecture bhv of shifter11 is
signal data_latched: std_logic_vector(10 downto 0);
if(rst='0') then
data_latched <= "11111111111";
elsif(shift_load_select = '1') then
data_latched <= data_in;
elsif(clk'event and clk='1') then
data_latched <= shift_in & data_latched(10 downto 1);
end if;
end process;
data_out <= data_latched(0);
end bhv;

We have isolated the CPLD completely with nothing but a clock pin +
reset as external input. With hard-coded input to the shift register
and another test entity that does nothing but sniff the ouput and
verify its correctness, we are occasionally running into problems.
After many thousands of shifts + outputs over 20-60 seconds, there will
be one or more bits flipped in the shift register output. 99.999% of
the time the output is correct, we just can't figure out why this thing
is failing.

The issue seems to only occur when we place multiple shift registers in
our design working in parallel, a single shift register alone will work
error-free. To me this seems to indicate a tool issue when utilizing
resources close to the limits of the chip.

Another possibility is a hardware problem, however we have double and
triple checked all ground / VCC pins and reduced the external inputs to
the bare minimum.

I started going through the generated postfit equations, however I
started to get a headache after about the 100th flip flop.

Any suggestions on how to fix this?

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