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Old 04-29-2006, 05:35 AM
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Default Re: Opteron HT coprocessors

c d saunter wrote:
> JJ ([email protected]) wrote:
> : In comp.arch (and others) there is a thread on this Opteron Virtex4
> : coprocessor that sits in socket 940.
> :
> :
> :
> : I wonder what others think of this, at $4500 its way to steep for most
> : individual buyers who might happen to have a dual socket Opteron board
> : (I don't), but I wonder if companies like Digilent, Enterpoint and
> : others might see any opportunity to build a much lower cost edu version
> : that is more in line with the cost of an Opteron cpu chip say <$1k and
> : based on best Spartan3 or Virtex2,4 that can still use Webpack.
> John,
> I expect the $4500 reflects development costs and what the market will
> bear more than anything else - after all the only thing I've seen near it
> was the old Pilchard FPGA on a DIMM research project.

Ofcourse, I recall Xilinx VC funded that or another FPGA-DIMM company,
not quite the right time.

> : I also wonder how much faster exactly the HT link is over any of the
> : PCI interfaces.
> HT can be implemented much faster than parallel PCI but perhaps more
> importantly when used with an Opteron is that it's much more tightly
> coupled to the CPU. Looking at the upcoming HT3 I feel the best is yet
> to come.

Much lower latency I hope.

> One of the posibilities that interest me is a V4 module sitting in a 940
> socket with some MGTs wired up (space is tight - I realise that!) - if
> you happen to be dealing in high speed data aquisition and processing on
> the bit/word and (large) frame level then a tightly coupled
> FPGA/commodity CPU system is really quite exciting.

Takes one back to when you could interface 68000s or whatever to your
custom logic or even wire wrap your own mobo, its been along time since
one could "touch" a processor.

Whats you acquisition area?

> cds
> : John Jakson
> : transputer guy

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