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Old 04-28-2006, 11:47 PM
Ed McGettigan
Posts: n/a
Default Re: Xilinx SystemACE on multi-FPGA board

Stephen Williams wrote:
>> 8) What exactly does this mean?
>> "The SystemACE driver is getting an error that the JTAG configurator
>> was unable to read the configuration stream from the CF."

> These are the error, status and control register contents when the
> Linux kernel discovers the error:
> The Linux kernel is 2.4.33-pre1 w/ the mvista SystemACE drivers
> for Linux 2.4.
> The error messages from the kernel driver are:
> CompactFlash write command failed
> CompactFlash sector failed to ready
> CompactFlash sector ID not found
> JTAG controller couldn't read configuration from the CompactFlash

I had a quick discussion with our Linux/UBoot expert and the SystemACE
designer as well as reading your original case that you filed with our
hotline and we believe that the SystemACE driver code that you are using
is resetting the SystemACE and causing another configuration of the
devices in the chain.

In the case of the single FPGA in the chain the SystemACE reconfiguration
may complete and return control to the MPU port before another MPU access
is made. While in the case of the two FPGAs in the chain the reconfiguration
is still occurring when you attempt another MPU access. In any case you
should not be reconfiguring the devices a second time (unless you really want to)
and our Hotline had given you instructions on how to prevent the reconfiguration.

If you would like to confirm this theory you can put a scope probe on the
CFG_TCK pin from SystemACE and you should see it actively toggle, stop for
a period of time after the 1st configuration and then restart again at some
point before stopping permanently.

>> 9) It sounds like you filed a case with our hotline, what number were
>> you assigned?

> Case # 628407
> (The webcase person asked none of these questions.)Our

The hotline engineer assign to your case did not ask any of these questions
that I posed as your original query was very different from the one that
you posed here on comp.arch.fpga, but I do believe that they did give you
an answer that will resolve the problem when you implement it.

Ed McGettigan
Xilinx Inc.
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