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Old 04-28-2006, 09:16 PM
Stephen Williams
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Default Re: Xilinx SystemACE on multi-FPGA board

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> Stephen Williams wrote:
>
> OK, Xilinx was uniquely unhelpful this time, so I resort to this
> list. My setup is a SystemACE connected to 1 or 2 Virtex2 FPGAs,
> and also to a PPC405GPr running Linux. The second FPGA is optional,
> and when the optional FPGA is installed, the JTAG is rerouted through
> and a different ACE file supplied. The CF card contains a second
> partition where the Linux fs (ext3) lives.


Ed McGettigan wrote:

> Not enough information on your problem.


> 1) In the single Virtex-II case, what does the complete JTAG chain look
> like?


ACE.TDO --> FPGA1.TDI
FPGA1.TDO --> ACE.TDI

> 2) In the dual Virtex-II case, what does the complete JTAG chain look like?


ACE.TDO --> FPGA1.TDI
FPGA1.TDO --> FPGA2.TDI
FPGA2.TDO --> ACE.TDI

> 3) Have your connected the DONE pins of the Virtex-II devices together?


Yes. The Init lines are also connected together and to the SystemACE.
I thought at first that they were not, but I was mistaken.

> 4) In the dual Virtex-II case, do both device go DONE?


Yes, although my test for that is to note that them both respond on
the PCI bus, and seem to function properly. Also, I note that I get
the CFGDONE bit in the STATUSREG before I continue from u-boot.
Oh, and they are Virtex-4, not Virtex-II. Although we have a V-II
variant of the board as well.

> 5) Which device is connected to the MPU port of the SystemACE device?


The PPC405GPr, through CS1#.

> 6) What holds the PPC405GPr in reset until both Virtex-II devices have
> been configured?


Nothing, the U-Boot bootstrap loader polls for the CFGDONE bit before
u-boot is allowed to proceed with reading the kernel from the FAT FS.

> 7) What exactly is a PPC405GPr, I think that this is discrete PPC405,
> but which one?


It is an IBM PowerPC405GPr. Part number IBM25PPC405GPR3BB333. We
do not use any internal 405 cores, we use a discrete part that has
PCI, SDRAM controllers, etc. The PCI bus of the PPC connects to
the FPGA[s], so the FPGA devices show up as PCI devices to Linux.


> 8) What exactly does this mean?
> "The SystemACE driver is getting an error that the JTAG configurator
> was unable to read the configuration stream from the CF."


These are the error, status and control register contents when the
Linux kernel discovers the error:
CONTROLREG=0x10a STATUSREG=0x19035e ERRORREG=0x2098

The Linux kernel is 2.4.33-pre1 w/ the mvista SystemACE drivers
for Linux 2.4.

The error messages from the kernel driver are:
CompactFlash write command failed
CompactFlash sector failed to ready
CompactFlash sector ID not found
JTAG controller couldn't read configuration from the CompactFlash


> 9) It sounds like you filed a case with our hotline, what number were
> you assigned?


Case # 628407
(The webcase person asked none of these questions.)

- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
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iD8DBQFEUmn7rPt1Sc2b3ikRAn5hAJ0VJ30nISbGFyU4+W2gPy gJghCFeQCeJ3F0
tEMY2tmyaM7vJgJkZvDwk6o=
=d8Vq
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