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Old 04-28-2006, 08:04 PM
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Default Re: Xilinx Virtex-4 OCM Usage Issues

Wow - this topic has got lots of activity. Ben, thanks for pointing
out the APU bits - I was aware of these and do have this value already
in place (I am running 7.1, although I keep thinking of trying 8.1).

As for interrupts, I just think that if I was hitting one that the OCM
or PLB busses would jump to that location and try to fetch the
instruction at the interrupt handler, on top of the fact that a simple
"move register" command shouldn't cause an interrupt to occur to begin
with. I'll keep the interrupt possability on the board to come back to
in case my current train of testing doesn't pan out.

At this point, I have disabled cache in order to remove one more
possible issue from the design.

The current train of thought I'm working on is getting an SDRAM/OCM
Virtex-4 system working on a Xilinx ML403 development board and
comparing it to my SDRAM/OCM system. So far I have got the LED test to
work out of SDRAM when running the core at 2x the PLB clock speed (my
system does 3x, but the dev board has issues running at 3x). So here
are the things I am going to try first

1) Try my system running at a 1:1 ratio
2) Try our customized PLB controller on the dev board

Hopefully, I can get some information out of these two steps...

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