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Old 04-28-2006, 02:01 PM
Ben Jones
Posts: n/a
Default Re: Xilinx Virtex-4 OCM Usage Issues

Hi Brian,

"Brian Drummond" <[email protected]> wrote in message
news:[email protected]

> >4) Yeah, the link register increments by 4, the PC/CTR registers are
> >correct and then register 5 is copied into register 6. I don't know
> >anything about how interrupts work on the PPC, so I'll have to read up
> >on that.

> Since Ben mentioned interrupts a couple of times, and you say this, let
> me point out one "gotcha" ... well it caught me out anyway...
> The register pointing to the interrupt vector table holds ONLY the 16
> MSBs of the vector table address.
> Thus putting the table at 0xffff4000 (as we did) doesn't work. You'd
> think the EDK tools might have warned about this, but nooo... they built
> the code just fine.
> ...
> IMO this limitation COULD have been more clearly documented, as well as
> trapped by the tools...

Good point. As far as documentation goes it took me a while to find where
this is explained (PowerPC Processor Reference Guide, Chapter 7 "Exceptions
and Interrupts", section "Interrupt-Handling Registers", EVPR, page ~204,
and also mentioned in the OS and Libraries Documentation, Standalone PowerPC
BSP section). :-) Do you have a suggestion as to where else you think this
should be mentioned, to make it more obvious?

The EDK tools do the Right Thing when generating the default linker script -
and Base System Builder will notify you if you don't have room for the
vector table in your project due to this limitation (e.g. you have < 64KB of
BRAM). I guess the linker could be modified to check what it's being asked
to do with the "vectors" section and barf (or at least issue a warning) if
the alignment is wrong, but this would be a bit of an ugly "special case"...



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