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Old 04-28-2006, 01:25 PM
Brian Drummond
Posts: n/a
Default Re: Xilinx Virtex-4 OCM Usage Issues

On 27 Apr 2006 11:53:22 -0700, "[email protected]"
<[email protected]> wrote:

>Yeah, it's been quite puzzling - I had the local Xilinx FAE out here
>the other day and we weren't able to get anywhere on it (besides
>agreeing that the PLB and OCM busses look like they should). So here
>are the answers to your questions, followed by the more recent

>4) Yeah, the link register increments by 4, the PC/CTR registers are
>correct and then register 5 is copied into register 6. I don't know
>anything about how interrupts work on the PPC, so I'll have to read up
>on that.

Since Ben mentioned interrupts a couple of times, and you say this, let
me point out one "gotcha" ... well it caught me out anyway...

The register pointing to the interrupt vector table holds ONLY the 16
MSBs of the vector table address.

Thus putting the table at 0xffff4000 (as we did) doesn't work. You'd
think the EDK tools might have warned about this, but nooo... they built
the code just fine.

Then the CPU took its first interrupt, and looked for a vector offset
from ffff0000, and couldn't find one. So it took an "illegal
instruction" interrupt, and went to ffff0700 to find the handler...

Moving the vector table to a 16 byte boundary (ffff0000 in our case)
solved the problem.

IMO this limitation COULD have been more clearly documented, as well as
trapped by the tools...

- Brian
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