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Old 04-27-2006, 08:53 PM
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Default Re: Xilinx Virtex-4 OCM Usage Issues

Yeah, it's been quite puzzling - I had the local Xilinx FAE out here
the other day and we weren't able to get anywhere on it (besides
agreeing that the PLB and OCM busses look like they should). So here
are the answers to your questions, followed by the more recent

1) We are just running out of flat memory space in priviledged mode.

2) We have a Green Hills probe to debug - I haven't tried using the XMD
program. The boot code is C. Code is copied from FLASH into SDRAM and
using the Green Hills probe, I am able to verify the contents of SDRAM.

3) When I stop the code the first time, it goes to 0x2004 and I can
still read/write reigsters. When I do a step or press run again, I get
something like a "Processor not stopped after single step" and then I
cannot read/write any register from the green hills probe command line.
From the green hills multi debugger, I get "timeout waiting for cre to
stop in read of GPR 30. Single Step Failed."

4) Yeah, the link register increments by 4, the PC/CTR registers are
correct and then register 5 is copied into register 6. I don't know
anything about how interrupts work on the PPC, so I'll have to read up
on that.

So the FAE suggested trying to break the problem down to eliminate the
boot code. To that end, I have taken a short program that prints
"entering code()" and "exiting code()" and then stops. I boot from
this code and using the debugger reset. So at this point, none of the
registers or memory have been setup. I use the debugger to load SDRAM
0x2000-0x200C (the first four instructions) and program the PC to
0x2000. If I load the design that uses the PLB RAM instead of the OCM
RAM and load the registers from the last example (none are set up) and
locations 0x2000-0x200C in SDRAM, I am able to step through all of
these instructions.

Thus, it seems like nothing is wrong with the software, with the
exception of not setting up a register value to enable the device to
switch from OCM to SDRAM. The fact that it boots correctly out of IOCM
and jumps to SDRAM at all, seems to indicate that the hardware logic is
in place.

I hope that helps clarify what we've got in place and points out what
I'm missing.


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