Thread: CLock Issue
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Old 04-27-2006, 06:13 PM
Ben Jones
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Default Re: CLock Issue

Hey Fizzy man,

"Fizzy" <[email protected]> wrote in message
news:[email protected] oups.com...
> If i have 100 MHz clock how can i generate a 200 Hz with 50% duty cycle
> clock.


Erm, a 19-bit counter?

Did you really mean 200Hz, or did you mean 200MHz? Why would your logic run
at 200Hz? You might want to think about using a clock-enable rather than a
separate 200Hz clock signal; that will be much easier for the design tools
to analyse.

> I think i have to use async FIFO to change the data between the
> different clock domains... I am not sure. Cna any buddy help in this..


If you really *did* mean 200Hz, then you would be best of using a simple
handshaking circuit, with enough buffering in it that the PLB doesn't get
tied up for milliseconds at a time by your incredibly slow circuit. This
could be an async FIFO, but it most likely doesn't need to be as complicated
as that (particularly given the huge differential between the two domains).

If you meant 200MHz, then you can generate that using a DLL (x2 output) and
the clocks will be related, so you can again manage without a FIFO (although
you will still have to design your circuit carefully).

-Ben-


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