Thread: CLock Issue
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Old 04-27-2006, 06:00 PM
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Default CLock Issue


If i have 100 MHz clock how can i generate a 200 Hz with 50% duty cycle

Let me explain why i need this.... I have a custome IP which will be
attached to PLB through IPIF block (using xilinx virtex4-FX). The IPIF
uses bus clock for data to be put in FIFO. But my logic runs at 200 Hz.
What i was thinking was to divide 100MHz clock to generate 200 Hz clock
and then clock the data in from IPIF block to my logic. I think i have
to use async FIFO to change the data between the different clock
domains... I am not sure. Cna any buddy help in this..


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