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Old 04-27-2006, 01:48 PM
Ben Jones
Posts: n/a
Default Re: Xilinx Virtex-4 OCM Usage Issues

Hi Charles,

<[email protected]> wrote in message
news:[email protected]
> Ben-
> Thanks for the suggestion - my explaination wasn't very clear: Our
> first iteration used a small BRAM on the PLB bus to boot, loaded SDRAM
> (which was defined as cached memory space), and then ran out of SDRAM.
> With the all the PLB arbitration and overhead logic, this resulted in a
> 4% of our virtex 4 (fx20). Currently, we're around 85% and would like
> to save this 4% to help build time and allow for future flexibility.

Thanks for the clarification. This is quite puzzling!

Are you using any of the memory protection features of the PowerPC, or is
this all running in a flat memory space in supervisor mode? Just to rule out
any odd effects due to TLB etc.

What are you using to debug the bootloader (GDB/source level, or raw XMD)?
Is the bootloader written in ASM or C? Where is the application code that is
written to SDRAM coming from (flash, I guess)? Does your bootloader verify
that the code has been transfered succesfully?

> if I step the processor, it gets lost and never returns.

If in XMD you then do a "stop", what happens? Do you get a "processor
stopped at 0xwha73v3r", or something like "target cannot perform the
operation"? Where do your interrupt vectors live (if in fact you have any)?

> the first instruction out of SDRAM is completed and then PPC405 stops

So your "bctrl" does the Right Thing (sets PC from CTR [which ==0x2000] and
stores PC+4 in LR), and then the "mr r6, r5" happens OK, and then the whole
thing goes up the creek, right? It sounds for all the world like it's taking
some interrupt vector into the middle of nowhere.

Sorry for the deluge of questions - you don't have to answer them all! I'm
just trying to get a feel for what your system looks like.



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