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Old 04-25-2006, 07:29 AM
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Default Re: ISE 8.1 Sub module Synthesis

On Tue, 25 Apr 2006 03:39:22 +0200, Gerhard Hoffmann
<[email protected]> wrote:

>On Mon, 24 Apr 2006 17:29:34 +0200, Zara <[email protected]> wrote:
>>I don't know if it will work in verilgo, but I soppes it will. It
>>works on VHDL. Right click on source node , "Select as Top Module". Do
>>remember to reselect original Top module when done.

>I did this, too (vhdl), but then the "real top module" user constraint file was
>changed to empty. Gave not so funny results with the router deciding arbitrarily
>which pin is wich. I had connected new hardware to the eval board and
>assumed that I had killed the Virtex4 :-(
>Luckily, it was too late already to order a new one.
>It would help if one could see in the log files what the reason was for a
>signal to end up at a certain pin.

Well, never tried it like that. I just limit all work to synthesis
when my tuop module is not *the top module*.

>Dependency checking seems to be messed up in 8.1 . That could be a
>reason for the above, too.
>Today, I got warnings about incompatible components and instantiatons.
>I removed some instantiations completely ( commenting out large
>blocks is _such_ a fun in VHDL..) but still they appeared in the error list.
>It looks like ISE has made own copies of my source files.
>I don't use the internal editor but gvim, so maybe ISE does not see every
>file update?

I use Crimson Editor, ans everything works fine.

>Using Project -> CleanupProjectFiles reduced the number of error messages
>by 80%, but not completely.
>And, because I'm in the mood: The ISE gui is almost dead after kicking
>off a synthesis. Sometimes, the routing has run to completion before
>the gui wakes up again. The first run after booting seems not to be
>affected by this. I use the windows task manager to keep track of
>what's going on (shows top CPU eating processes).

It is the "feature" of reading all reports to create the desgin
summary. It is nice, but it is a heavy load.

BTW, I run ISE on an athlon dual core machine, and it is funny to see
50% of the "CPU" (that is, a full core) used up by
synthesis/xlate/map/par while the other 50%( the other full core) is
used byISE itself to keep reports updated. Most ilustrating.

>When I double click on "ConfigureDevice" to kick off synthesis & everything,
>and do 5 times edit-compile-load-measure, then I end up with 5 incarnations of
>IMPACT, as if one wasn't enough, and each one asking me what to do and
>if it should update the project file on exit, as if anything had changed.

Yes, that is really stupid.

>ISE knows enough about my project so that one doubleclick should be enough
>to go from source to logic analyzer. We had that already in XC3020 times.
>Impact should not ask ME if it needs a mask file for verify.


>I changed from 7.1 to 8.1 because 7.1 crashed may computer abt. 6 times
>a day. Those crashes are history with 8.1, but all in all, things have
>gone from bad to worse.
>Retreating to 6.3 like others here do is probably no option for a virtex4.
>Perhaps I should convert everything to makefiles.

Best luck. I use only Spartan3, and I can keep up with some of these
nuisances. Going back is not a choice.

Best regards.

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