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Old 04-25-2006, 12:15 AM
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Default Xilinx Virtex-4 OCM Usage Issues

Hello to the group!

I've been struggling to get the Xilinx IOCM and DOCM modules working
with the PPC405 in my current design and I'm starting to run out of
ideas. The first iteration of the design uses cached SDRAM via the PLB
to store/load the boot code and runs without issue. Since the design
is starting to get full (running out of LUTs, but BRAMs are available),
it was decided that it might be worthwhile to use the OCM interface to
cut down on logic. The OCM should be the perfect solution because the
boot code is currently only called once and then code executes out of
SDRAM.

I have been able to get the OCM modules connected and currently the
boot code makes it through without issue. The problem occurs just
after the conditional jump to SDRAM: the first instruction out of SDRAM
is completed and then PPC405 stops. I have been able to connect via a
debugger and everything appears to be fine at the stopped location, but
if I step the processor, it gets lost and never returns. I am not sure
why it stops at this point (See code below).

I have gone through the OCM/Virtex-4 information and everything seems
ok:
* The errata 212/213 fix is in place
* Cache is disabled (cache was working fine on the first design)
* I have compared all the PPC registers at the point of failure with
the values from the first iteration and have found no major
unexplainable differences
* I have added a PLB_IBA core and observed that the OCM design loads
the first four instructions from SDRAM after completing the boot code.
I have verifed that these instructions are correct. After this point,
however, there is no more activity on the PLB nor the OCM busses
* An ILA on the OCM bus showed that the instructions stop being
executed by the IOCM following the jump (and it looks like a few extra
instructions are loaded from IOCM because of the conditional branch)
* Neither the ILA nor the PLB_IBA cores showed an error/abort occuring.
The debugger did not indicate that any exceptions had occurred
* I have tried changing the OCM values (range checking/fixed
latency/auto-detect clocking), but this seems to make no difference

* The memory map used:
SDRAM 0x0000 0000 - 0x01FF FFFF
DOCM 0x2080 0000 - 0x2080 1FFF
IOCM 0xFFFFC000 - 0xFFFF FFFF

* The Assembly code is nothing fancy:
....
0xffffca2c main+0x258: 7c0903a6 mtctr r0 <entryPt>
0xffffca30 main+0x25c: 4e800421 bctrl
0x2000: 7ca62b78 mr r6, r5
0x2004: 7c852378 mr r5, r4
....

Basically it seems like the bus is hooked up correctly, but that maybe
a register bit or mode is not correct. I am wondering if anyone in
this forum has the IOCM/DOCM working and also executes code out of
SDRAM (or anyone else who has comment) - are there any register bits
that I might have left out? Does software have to do anything
differently now that the design is non-cached (I have tried
initializing all cached registers...)?

Thanks,
-Charles Eddleston

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