View Single Post
  #2 (permalink)  
Old 04-24-2006, 05:29 PM
Zara
Guest
 
Posts: n/a
Default Re: ISE 8.1 Sub module Synthesis

On Mon, 24 Apr 2006 10:58:46 -0400, Eli Hughes <[email protected]> wrote:

>Hello:
>
>I ran into an issue (which may be a 'feature') in version 8.1 of ISE.
>When I have a simple verilog project with a top level module, I can no
>longer right click on one of the sub verilog modules for synthesis. In
>previous versions (7.1, etc) I could right click on any of the sub
>modules and syntehsize them indivdually. In 8.1 the only processes I
>have for a submodule are to check syntax, generate schematic symbol and
>view instantiation template.
>
>
>This is a real annoyance as it is nice to add submodules to my project
>to synthesize/simulate them indivually before integrating them into my
>top level module. If there a way to turn this 'feature' off?
>
>-Eli



I don't know if it will work in verilgo, but I soppes it will. It
works on VHDL. Right click on source node , "Select as Top Module". Do
remember to reselect original Top module when done.

I should classify it a s a real feature, because you can bypass it
when needed, but you save time when double clicking on Synthesis with
the wrong node selected.

Best regards,

Zara
Reply With Quote