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Old 04-24-2006, 04:58 PM
Eli Hughes
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Default ISE 8.1 Sub module Synthesis


I ran into an issue (which may be a 'feature') in version 8.1 of ISE.
When I have a simple verilog project with a top level module, I can no
longer right click on one of the sub verilog modules for synthesis. In
previous versions (7.1, etc) I could right click on any of the sub
modules and syntehsize them indivdually. In 8.1 the only processes I
have for a submodule are to check syntax, generate schematic symbol and
view instantiation template.

This is a real annoyance as it is nice to add submodules to my project
to synthesize/simulate them indivually before integrating them into my
top level module. If there a way to turn this 'feature' off?

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