radarman schrieb:
> Where I work, we aren't allowed to directly connect FPGA or CPLD pins
> directly to external connectors, save for on-board test points (like
> Mictor connectors). Everything goes through external buffers or
> registers. Yes, it does add latency, but it does protect
> hard-to-replace BGA's from damage.
>
> Of course, I work on military hardware, and reliability is a major
> factor. While most things are replaced at LRU (chassis) level, there
> are some systems where the customer is allowed to replace individual
> boards. Usually, this happens in a customer repair facility, and is
> done by military technicians, but still - it pays to go the extra mile.

I thought in military applications reliability is more important than
cost. For standard buffers I would argue that you get a much higher
failure rate with the buffers than without. You have three times the
number of solder joints and much more parts after all.
Also, many buffer chips are less robust then FPGA pins. Some don't
even have protection diodes.
Of course if you use special ESD protection buffers all this changes.
But some passive protection to the FPGA pin might give you the same effect.

> The other factor is that every board costs so much, that they are
> almost never thrown away, and instead reworked. It is much simpler to
> replace a buffer chip than a BGA.

With the right tools it is not really more complicated to replace a bga
or an SOIC. Local IR-heating, pulling the chip, cleaning the board,
placing a new chip, local IR-heating again.
Cleaning takes longer because there are more pads. But that's about it.
I doubt that the cost of replacing the BGA is more than 5% of the cost
of isolating the defect.

Kolja Sulimma