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Old 04-21-2006, 03:08 PM
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Default Re: Initializing array of BlockRAM instances in verilog

[email protected] wrote:
> Hi,
> I'm trying to create an array of Virtex-II BlockRam instances in
> verilog using
> RAMB16_S36_S36 BRAM[ram_modules-1:0] (.ADDRA(ADDRA), .ADDRB(ADDRB),
> ..., .DOPA(), .DOPB());
> This works perfectly fine, even when I add parameters like:
> RAMB16_S36_S36 #(.WRITE_MODE_A("READ_FIRST")) BRAM[ram_modules-1:0]
> (.ADDRA(ADDRA), ...
> However, when I add the initialization parameters, it doesn't work:
> RAMB16_S36_S36 #(.WRITE_MODE_A("READ_FIRST"), .INIT_A(36'h012345678))
> BRAM[ram_modules-1:0] (.ADDRA(ADDRA), ...
> Compiling is ok, but trying to simulate gives one of these for each
> module in the array:
> # ELAB2: Warning: ELAB2_0048 increment.v (22): Actual value is
> incompatible with formal "INIT_A" (mixed simulation) - actual value
> will be skipped.
> in Aldec Active-HDL.
> I've tried a bunch of different ways to get this to work.
> Initialization using the defparam statements with just one BRAM
> instance works fine (but not on an array, at least that I can figure
> out). I guess I could just unroll the whole thing by hand, but by now,
> I'm interested in just figuring out what's going on and how to make it
> work.
> Anyone else run into this or have any ideas?
> Much thanks
> -Allan

Is it possible that the initialization values are not replicated like
the module ports? i.e. for an array of 2 BRAMs maybe you
need to give 72 bits of INIT_A instead of 36?

..INIT_A(72'h012345678012345678)) BRAM[ram_modules-1:0] (.ADDRA(ADDRA),

Good luck,

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