View Single Post
  #16 (permalink)  
Old 04-21-2006, 01:45 PM
rickman
Guest
 
Posts: n/a
Default Re: Spartan 3 chips in power up

Jeff Brower wrote:
> Rick-
>
> If it's any consolation, we went through S3 pull-up/pull-down hell last
> summer. We ended up putting a few additional values on the board that
> we thought the S3 should have been able to handle internally. We also
> found significant variation between S3 devices.
>
> We also found issues with multi-FPGA configuration from platform Flash
> vs. temperature that required some undocumented FPGA-related board mods
> that my company won't disclose, as it took us nearly 6 weeks to get it
> nailed down.


Thanks for the info, but your troubles are never consolation for mine.
Considering that the Spartan 3 pullups are so stiff, I find it
negligent that Xilinx would not document the fact that they put them on
the mode pins. Unless you typically use *very* stiff resistors or just
plain use 0 ohm jumpers for pulldowns, the mode pins will not work.
Xilinx knows this and still has not put it in the data sheet that I can
find. I just downloaded the data sheet and it was just updated this
month. The answer record that describes the pulldown problem is over a
year old! Don't you think a year is enough time to get the facts
straight in a data sheet, especially on such a basic and important
issue???

Reply With Quote