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Old 04-19-2006, 07:38 PM
Symon
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Default Re: Is there anything fundamentally wrong with this code?

<[email protected]> wrote in message
news:[email protected] oups.com...
> Thanks for your response,
>
> This code snippet is actually a structural representation of my actual
> code (which is much more complex). I am experiencing some strange
> behaviour where although 'input_signal' is only held high for one clock
> cycle (by another process, but using the same clock) the
> 'output_signal' is asserted twice, or so it appears. I was wondering if
> the structure of my code (and my coding style) would cause this
> situation to occur. It only appears to present itself on
> 'real-hardware' in the 'simulator' I cannot repeat the strange
> behaviour.
>

Hi Simon,
Is it in a device with a soft logic analyser available like Chipscope? Are
any of the inputs asynchronous to the clock?
Cheers, Syms.


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