View Single Post
  #2 (permalink)  
Old 04-19-2006, 01:28 PM
Posts: n/a
Default Re: Is there anything fundamentally wrong with this code?

I noticed that local_signal gets set in two seperate if - end if sections.
If both sections are true, the second one wins, IIRC. This can be confusing,
so I endeavour to avoid this in my code. You might want to merge the two
sections with an else.

You could always try simulating it with a testbench to check you get what
you want? Or code it as a FSM so it's more readable?

BTW, I recommend using rising_edge(clock) instead of that clock'event stuff.
It not only saves typing but works better in simulations when things can
change from other than '0' to '1'.

Finally, do you know about comp.lang.vhdl? They love this stuff! :-)
HTH & Cheers, Syms.

Reply With Quote