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Old 04-18-2006, 03:27 PM
John_H
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Default Re: Implementation of cascadable shift register in virtex FPGA

prav wrote:

> Hi all,
>
> I was going through the datasheet of virtex2 , in which i read that
>
> "each 4-input function generator is programmable as a 4-input LUT, 16
> bits of distributed SelectRAM memory, or a 16-bit variable- bits of
> distributed SelectRAM memory, or a 16-bit variable-tap shift register
> element."
>
> In the diagrams given in the viretx2 datasheet for cascadable shift
> register , i don't seen any clock at all.
>
> Can anybody clarify on this implementation???
>
> Regards,
> Prav


See, specifically, Figure 21 on page 16 of "Module 2: Functional
Description" (pdf page 24) from v3.4 of the "Virtex-II Complete Data
Sheet (All four modules)"

http://direct.xilinx.com/bvdocs/publications/ds031.pdf

Where the DI and WS are illustrated on the LUT with the write strobe
generated as "WSG" from the Write Enable and Clock.
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