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Old 04-17-2006, 03:43 PM
Posts: n/a
Default Re: How to apply timing constrains for large bus

vssumesh wrote:
> One more doubt....
> Tried to decrease the fanou by introducing bufferes for the
> selection pins to the Mux. But it is not in the final output The Map is
> optimizing the buffers away. It is listed in the xilinx library guide
> also. But then how can we reduce the fanout or introduce extra
> buffering....

If the fanout of the select is your biggest problem, don't "buffer"
those signals but replicate the registers. You need to talk the
synthesizer into leaving the replicated logic in your design; in
SynplifyPro I'd use the syn_preserve directive to keep those replicated
registers in my design.

If you can pipeline your 50:1 mux you can keep the performance and the
simple mux structure rather than time-multiplexing a multiplex which...
shouldn't produce any net benefit.
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