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Old 04-17-2006, 02:12 PM
Brian Davis
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Default Re: Did National cheat with the Virtex 4

[email protected] wrote:
>
> I agree with what you wrote, however the video actually shows the
> 750MHz LVDS output and they talk about it running at this speed.
>


I watched the video, but offhand, I don't recall them actually showing
the clock the to FPGA at 750 MHz, other than at the viewgraph level-
which segment of the video is that 750 MHz reference in?

If you look at Nationals app note:
http://www.national.com/signalpath/f...esigner103.pdf

Page 7 shows the 1/4 Fs clock being used to clock the FPGA
at Fs=1GHz, Fddr=250 MHz

Brian

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