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Old 04-15-2006, 05:03 AM
John Larkin
Posts: n/a
Default Re: humble suggestion for Xilinx

On Sat, 15 Apr 2006 10:45:06 +1200, Jim Granville
<[email protected]> wrote:

>John Larkin wrote:
>> Since the max serial-slave configuration rate on things like Spartan3
>> chips is, what, 20 MHz or something, you might consider slowing down
>> the CCLK input path, and/or adding some serious hysteresis on future
>> parts. On a pcb, CCLK is often a shared SPI clock, with lots of loads
>> and stubs and vias and such, so may not be as pristine as a system
>> clock. CCLK seems to be every bit as touchy as main clock pins, and it
>> really needn't be.

>Wouldn't one expect this to be 'normal design practise' ?
>I suppose Xilinx missed that obvious feature, becasue there are no
>other Schmitt cells on the die, and even tho the CPLDs have this,
>I'm sure their inter-department sharing is like most large companies

I have it secondhand (one of my guys tells me) that all S3 inputs have
about 100 mV of hysteresis. But that's not enough to improve noise
immunity in most practical situations.

It's good that FPGAs keep getting faster, but not all applications
need all that speed, and pickiness about clock edge quality can be a
real liability in a lot of slower applications.


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