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Old 04-14-2006, 03:53 PM
John Larkin
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Default Re: humble suggestion for Xilinx

On Fri, 14 Apr 2006 05:53:30 GMT, John_H <[email protected]>
wrote:

>John Larkin wrote:
>>
>> Since the max serial-slave configuration rate on things like Spartan3
>> chips is, what, 20 MHz or something, you might consider slowing down
>> the CCLK input path, and/or adding some serious hysteresis on future
>> parts. On a pcb, CCLK is often a shared SPI clock, with lots of loads
>> and stubs and vias and such, so may not be as pristine as a system
>> clock. CCLK seems to be every bit as touchy as main clock pins, and it
>> really needn't be.
>>
>> John

>
>John,
>
>Are your suggestions for the CCLK generated by the Xilinx device or the
>CCLK received by the Xilinx device?
>


In serial-slave mode, the FPGA receives CCLK.

>I think the max speed is up to 66 MHz these days in the Spartan3E. It
>may not be LVDS rates but it's not 4000 series logic, either.


Right. Improving the noise immunity of the CCLK receiver would have
exactly one practical result: more FPGAs would configure.

John


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