View Single Post
  #2 (permalink)  
Old 04-14-2006, 07:53 AM
John_H
Guest
 
Posts: n/a
Default Re: humble suggestion for Xilinx

John Larkin wrote:
>
> Since the max serial-slave configuration rate on things like Spartan3
> chips is, what, 20 MHz or something, you might consider slowing down
> the CCLK input path, and/or adding some serious hysteresis on future
> parts. On a pcb, CCLK is often a shared SPI clock, with lots of loads
> and stubs and vias and such, so may not be as pristine as a system
> clock. CCLK seems to be every bit as touchy as main clock pins, and it
> really needn't be.
>
> John


John,

Are your suggestions for the CCLK generated by the Xilinx device or the
CCLK received by the Xilinx device?

I think the max speed is up to 66 MHz these days in the Spartan3E. It
may not be LVDS rates but it's not 4000 series logic, either.

- John_H
Reply With Quote