View Single Post
  #1 (permalink)  
Old 04-14-2006, 04:52 AM
John Larkin
Posts: n/a
Default humble suggestion for Xilinx

Since the max serial-slave configuration rate on things like Spartan3
chips is, what, 20 MHz or something, you might consider slowing down
the CCLK input path, and/or adding some serious hysteresis on future
parts. On a pcb, CCLK is often a shared SPI clock, with lots of loads
and stubs and vias and such, so may not be as pristine as a system
clock. CCLK seems to be every bit as touchy as main clock pins, and it
really needn't be.


Reply With Quote