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Old 04-10-2006, 04:30 PM
Ralf Hildebrandt
Posts: n/a
Default Re: How to handle the high fanout

[email protected] wrote:

> I implement the design using xilinx device, and one net has high
> fanout,

=> The synthesis tool gives you a hint, that using a (manually inferred)
buffer may be not a bad idea. What buffers are available strongly
depends on the target architecture. Sometimes the synthesis tool will
infer such buffers automatically, if needed.

> so I duplicate the register, but it does not work, the net
> fanout remains the same.

> process(clk)
> begin
> if clk'event and clk = '1' then
> regenr <= regen;
> regenr2 <= regen;
> end if;
> but the timing analyzer still reports that regenr2 has the same fanout
> as the regenr did.

regenr and regenr2 are equal for the synthesis tool.

> I am confused and I wonder whether there was some settings that should
> be modified in ISE, or I should add some constraints in UCF file to
> achieve this?

If you have a synchronous design everything should be done
automatically, because the synthesis tool estimates the delay of the
high-fanout net, infers the appropriate logic and reports the resulting
clock frequency. Because of this high-fanout net the frequency may not
be very high. (So the warning is a hint for you to search for the reason
for the low frequency.)

Constraining the clock is the most important thing you need to do.

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