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Old 04-10-2006, 01:45 PM
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Default How to handle the high fanout

I implement the design using xilinx device, and one net has high
fanout, so I duplicate the register, but it does not work, the net
fanout remains the same.

The original code is:

process(clk)
begin
if clk'event and clk = '1' then
regenr <= regen;
end if;

I modified to be:

process(clk)
begin
if clk'event and clk = '1' then
regenr <= regen;
regenr2 <= regen;
end if;

but the timing analyzer still reports that regenr2 has the same fanout
as the regenr did.

I am confused and I wonder whether there was some settings that should
be modified in ISE, or I should add some constraints in UCF file to
achieve this?

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