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Old 04-05-2006, 04:37 PM
John_H
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Default Re: Delay value for FDDRCPE in Virtex-II Pro FGPA

100ns is 10 MHz. This isn't correct. What do you see that tells you "100
ns?" ...tool, verbiage.

"Milind" <[email protected]> wrote in message
news:[email protected] oups.com...
> Hi,
>
> I found that the delay value of the element FDDRCPE is 100 ns after
> running a timing simulation.
>
> Is it supposed to be so high?
> (to confirm it, I also ran a separate simulation of this single element
> and with different clk frequencies)
>
> FDDRCPE is "Dual Data Rate D Flip-Flop with Clock Enable and
> Asynchronous
> Preset and Clear", used when interfacing DDR with FPGA. It is present
> in the simlibs library.
>
> I'm using ISE 8.1 (and found the same thing in 7.1 too)
>
> If it is supposed to be that high, what may be the reason behind it?
>
> See a related post here:
>
> http://groups.google.co.in/group/com...426daa7240b82e
>
> Thanks and Regards,
> Milind
>



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