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Old 12-07-2005, 07:28 AM
Posts: n/a
Default Re: Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model

Thanks very much for your replies and suggestions.

At this moment, I do not have the development kit with me, so I cannot
continue testing of my design on the FPGA. Thus, any changes I make
cannot be programmed and checked. When I get the board back from my
colleagues, I'll try out your suggestions at once.

I do understand what you mean. That's why I thought it was baffling
that the behavioural model was transferred onto the FPGA, because I ran
Translate, MAP and PAR. I simulated all verilog models (behavioural,
post-translate, post-map and post-PAR). The post-translate, post-map
and post-PAR simulations results were the same, but they differ from
the behavioural model. Initially, when I tested the outputs using a
digital oscilloscope, the results I got seemed to match the behavioural
model, and not the post-translate, model or PAR.

To answer your questions,
(1) I'm not sure if I understood your first question but all verilog
models were simulation output from ISE. The behavioural model follows
the RTL which I wrote.

(2) Yes, my model has signal relationsips defined by clock edges. The
models synthesised OK. There were several warnings, but the severity is
very low.

(3) It read an NGC file. I'm afraid I do not know what this means,
because I'm very new at FPGAs and hardware design. Please see below for
the translation report:


Command Line: ngdbuild -intstyle ise -dd c:\rtl_fpga/_ngo -uc test.ucf
xc2s300e-fg456-6 test.ngc test.ngd
Reading NGO file 'C:/rtl_fpga/test.ngc' ...
Applying constraints in "test.ucf" to the design...
Checking timing specifications ...
Checking expanded design ...
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 53236 kilobytes
Writing NGD file "test.ngd" ...
Writing NGDBUILD log file "test.bld"...


I did output the internal clocks to pins to monitor the results. The
internal clocks and signals work OK, but the outputs were not as

Unfortunately, I encountered another problem. Like I mentioned before,
I currently do not have the FPGA development board with me, so I can't
continue to do any checking of signals. I made some changes to the
design in RTL, and after synthesis, translate, map and PAR, I ran a
simulation on all the verilog models. The behavioural model worked as
expected. However, the post-translate, map and PAR models were wrong.
There were no errors nor timing violations during synthesis. There were
also no errors in design translate, map and PAR. Could the problem be
in my pin assignment? There were no errors there though. I didn't use
the Xilinx PACE, but LOCed my input/output pins instead.

Any suggestions? Please feel free to ask for any more information, as I
do not know what to add, as I did not encounter any errors. Again,
please forgive the triviality of the questions as I am very new to

Thanks very much in advance for all your help. Appreciated


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