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Old 12-04-2005, 08:02 PM
Jim Wu
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Default Re: Virtex 4 IDELAY implementation

> I'm currently doing some tests on an ML461 board, using IDELAY to
> shift in some DDR signals. I am shifting 80 signals in groups of 8.
> Unfortunately, some signals do not get shifted, i.e. some of the
> IDELAY module do not seem to respond to INC & CE. I'm seeing this
> in chipscope. I have tried (1) instantiating a single IDELAYCTRL, then
> let the tool replicate the rest and (2) instantiating all IDELAYCTRL
> and manually assigning them to the
> appropriate regions. It didn't help.
>
> Has anyone encountered such behaviour?
>
> I also found this on the xilinx website:
>

http://www.xilinx.com/xlnx/xil_ans_d...PagePath=20125
>
> Does this mean that I have to invert the clock going into the IDELAY
> block?


This is one solution. The other solution is to constrain the design so that
the IDELAY control signals meet the half clock period timing.
Either way, you need to use separate timing contraints on the IDELAY control
signals so the timing analyzer will correctly analyze the timing on those
paths.

HTH,
Jim


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