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Old 12-03-2005, 03:46 PM
John Adair
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Default Re: Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model

Chloe

You left out a few facts that might help the group understand where your
problem has come from.

(1) The behavoural model - was this a simulation output from ISE e.g. post
translate model or one that you have written independently?

(2) Did your model have signals relationships defined by timing
relationships or by clock edges? Could it have been a model that might
synthesise?

(3) Do you have a macro (edif, ngc etc) that ISE might have picked up
instead of the behavioural model? Translate report should tell you that.

One thing to check is that you are not picking up a locally stored copy
rather than one from a remote directory if that is what you are expecting.
One trick if you are getting the unxpected is to change something in the
design file that you can easily monitor in the real world, e.g. output your
internal clock to a pin, and if that does not happen you know you are
picking up something unexpected.

Another thing to check is if increment synthesis is turned off in XST. There
have been issues with this I believe. Finally if you have not loaded any
service packs you should do so. Service pack 4 is the latest and can be
loaded direct without loading any of the prior service packs.

John Adair
Enterpoint Ltd. - Home of Raggedstone1. The Low Cost FPGA Development Board.
http://www.enterpoint.co.uk


"Chloe" <[email protected]> wrote in message
news:[email protected] oups.com...
> Calling all FPGA experts!
>
> I'm currently using Xilinx ISE 7.1i with the ModelSim XE III/Starter
> 6.0a simulator. The FPGA which I am downloading my design onto is a
> Spartan IIE (it's on the Spartan IIE LC Development Kit, with an
> XC2S300E device).
>
> After synthesizing, implementing and programming the design onto the
> FPGA, I tested the outputs of the FPGA on the development kit using a
> digital oscilloscope. However, I was not getting the signals I wanted.
> After simulating the design on ModelSim, and comparing the simulated
> outputs with the actual FPGA outputs, I realised that the behavioral
> model of the design was somehow transferred onto the FPGA, instead of
> the place-and-routed model.
>
> I checked the synthesis report, but there were no errors. There were
> some warnings, but they were unimportant (certain ports were assigned
> but not used), thus, neglected at the moment. There were also no timing
> violations. I also checked all the reports under "Implement Design",
> and there were no errors.
>
> Can anyone tell me why the behavioral model was transferred onto the
> FPGA instead of the place-and-routed model? Is that even possible? Can
> anyone advise me on the methods of overcoming this problem?
>
> I'd be happy to provide any extra information you need.
>
> Thanks very much in advance.
>
> Regards,
> Chloe
>



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