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Old 12-02-2005, 05:03 PM
Ryan Jones
Posts: n/a
Default Re: Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model

Chloe ,

I am pretty sure it is impossible to have the behavioral model
transferred to the FPGA. When you generate the JTAG file it runs
Translate, MAP and PAR first. Most likely, you are using modelsim with
the behavioral model instead of the place and route model. Make sure
you choose simulate post place and route model in your testbench. If
you are then there is some timing discrepency that modelsim is not
noticing that is causing the outputs of the FPGA to differ. Another
possibility is to make sure that you are not loading an old programming
file. This is a common problem. Regenerate the program file, noting the
time when it ran, and make sure the file you program is timestamped
with the same time.


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