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Old 12-02-2005, 09:15 AM
kyeyk
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Default Virtex 4 IDELAY implementation

Hi

I'm currently doing some tests on an ML461 board, using IDELAY t
shift in some DDR signals. I am shifting 80 signals in groups of 8
Unfortunately, some signals do not get shifted, i.e. some of th
IDELAY module do not seem to respond to INC & CE. I'm seeing thi
in chipscope. I have tried (1) instantiating a single IDELAYCTRL, the
let the tool replicate the rest and (2) instantiating all IDELAYCTR
and manually assigning them to the
appropriate regions. It didn't help.

Has anyone encountered such behaviour

I also found this on the xilinx website
http://www.xilinx.com/xlnx/xil_ans_d...tPagePath=2012

Does this mean that I have to invert the clock going into the IDELA
block

Thanks in advanc

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