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Old 12-02-2005, 09:37 AM
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Default Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model

Calling all FPGA experts!

I'm currently using Xilinx ISE 7.1i with the ModelSim XE III/Starter
6.0a simulator. The FPGA which I am downloading my design onto is a
Spartan IIE (it's on the Spartan IIE LC Development Kit, with an
XC2S300E device).

After synthesizing, implementing and programming the design onto the
FPGA, I tested the outputs of the FPGA on the development kit using a
digital oscilloscope. However, I was not getting the signals I wanted.
After simulating the design on ModelSim, and comparing the simulated
outputs with the actual FPGA outputs, I realised that the behavioral
model of the design was somehow transferred onto the FPGA, instead of
the place-and-routed model.

I checked the synthesis report, but there were no errors. There were
some warnings, but they were unimportant (certain ports were assigned
but not used), thus, neglected at the moment. There were also no timing
violations. I also checked all the reports under "Implement Design",
and there were no errors.

Can anyone tell me why the behavioral model was transferred onto the
FPGA instead of the place-and-routed model? Is that even possible? Can
anyone advise me on the methods of overcoming this problem?

I'd be happy to provide any extra information you need.

Thanks very much in advance.


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