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Old 11-23-2005, 04:25 AM
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Default Re: Disabling Xilinx clock enable usage...

Since my 'sig3' vector is four bits wide, the signal from the CE logic
needs to
fan out to the 4 flip flops. Now we get routing delay.

Antti's example may be correct, but for the 4 bit wide destination, I
I get a performance penalty.

I love synthesis, but... It sure would be nice to have any easier way
direct it! In any event, it sure beats schematics.

John Providenza

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