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Old 11-23-2005, 04:16 AM
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Default Re: Disabling Xilinx clock enable usage...

JustJohn wrote:
> Duane wrote:
> > johnp wrote:
> >> The suggestion to recode the Verilog to look like:
> >> always @(posedge clk)
> >> sig4 <= (sig1 & ~sig2) ? sig3 : sig4;
> >>
> >> concerns me since a smart synthesizer would recognize this to be
> >> EXACTLY the sime code, just written in an odd way.

> >That would require that the synthesis tool specifically look for the
> >default value on the right be the same signal as is being assigned to.
> >While I suppose it is possible that a synthesis tool might do that, I
> >kind of doubt it.

>
> I'd bet it would. I am continually amazed at how good the synthesis
> optimizers are getting.


The OP is using XST 6.2.03. It's not that smart.

Regards,
Allan.

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