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Old 11-23-2005, 02:57 AM
JustJohn
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Default Re: Disabling Xilinx clock enable usage...

Duane wrote:
> johnp wrote:
>> The suggestion to recode the Verilog to look like:
>> always @(posedge clk)
>> sig4 <= (sig1 & ~sig2) ? sig3 : sig4;
>>
>> concerns me since a smart synthesizer would recognize this to be
>> EXACTLY the sime code, just written in an odd way.

>That would require that the synthesis tool specifically look for the
>default value on the right be the same signal as is being assigned to.
>While I suppose it is possible that a synthesis tool might do that, I
>kind of doubt it.


I'd bet it would. I am continually amazed at how good the synthesis
optimizers are getting.

OP can probably force the results he's asking for by using a 'keep'
attribute, if he really wants to. I don't know how to express it in
Verilog, but the VHDL code follows. See 'KEEP' in the constraints guide
for Verilog syntax.

I couldn't resist on this one, had to do the experiment, and Antti is
100% right in this instance. P/R into an XC2V40-5 with CE logic in the
same LUT along with the CE MUX gives _slower_ results than putting only
the CE logic into a LUT and using the CE pin and and its built-in CE
MUX:

Using CE pin: under 2 ns.
Using LUT : over 2 ns.

An odd thing is that XST infers 2 FFs for the LUT version.
(Did someone say pushing a rope?)

Nice that the synthesis tools keep getting better, and there are less
opportunities to second guess them.

Regards,
John

entity CE_Inferral is
Port ( clk : in std_logic;
rst : in std_logic;
a_in : in std_logic;
b_in : in std_logic;
c_in : in std_logic;
q_out : out std_logic);
end CE_Inferral;

architecture Behavioral of CE_Inferral is
signal q : std_logic;
signal a : std_logic;
signal b : std_logic;
signal c : std_logic;
signal d_lut : std_logic;
attribute keep : string;
attribute keep of d_lut : signal is "true";
begin
q_out <= q;
--d_lut <= c when a = '1' and b = '0' -- Uncomment these two lines
-- else q; -- for 'CE' in LUT logic (slower)
process( clk )
begin
if RISING_EDGE( clk ) then
a <= a_in; -- sync port inputs
b <= b_in;
c <= c_in;
if rst = '1' then
q <= '0';
else
-- q <= d_lut; -- Uncomment this 1 line for 'CE' in LUT logic
if a = '1' and b = '0' then -- Uncomment these 3 lines
q <= c; -- to use CE pin on FF with only
end if; -- 'a and not b' function in a LUT
end if; end if;
end process;
end Behavioral;

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