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Old 11-23-2005, 01:20 AM
Duane Clark
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Default Re: Disabling Xilinx clock enable usage...

johnp wrote:
> All -
>
> Of course, I realize that my code sample REALLY wants to map to the
> Enable pin:
> always @(posedge clk)
> if (condition)
> sig4 <= sig3;
>
> The suggestion to recode the Verilog to look like:
> always @(posedge clk)
> sig4 <= (sig1 & ~sig2) ? sig3 : sig4;
>
> concerns me since a smart synthesizer would recognize this to be
> EXACTLY the sime code, just written in an odd way.


That would require that the synthesis tool specifically look for the
default value on the right be the same signal as is being assigned to.
While I suppose it is possible that a synthesis tool might do that, I
kind of doubt it. That would seem to me to require that the tool
designer deliberately coded the tool to de-optimize (is that a word
the code.

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