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Old 11-23-2005, 12:22 AM
johnp
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Default Re: Disabling Xilinx clock enable usage...

All -

Of course, I realize that my code sample REALLY wants to map to the
Enable pin:
always @(posedge clk)
if (condition)
sig4 <= sig3;

The suggestion to recode the Verilog to look like:
always @(posedge clk)
sig4 <= (sig1 & ~sig2) ? sig3 : sig4;

concerns me since a smart synthesizer would recognize this to be
EXACTLY
the sime code, just written in an odd way.

The safest approach (which I've change to) is to add another level of
pipelining.

It just seems sad that even when the LUTs are available, the
synthesizer put
in an extra logic level so it could use the Enable pin.

BTW, this is with XST 6.2.03. It could be that the newer versions are
better.

John Providenza

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